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description the CXP854P60 are a highly integrated micro- computers composed of a 8-bit cpu, prom, ram, and i/o ports. these chips feature many other high- performance circuits in a single-chip cmos design, including an a/d converter, serial interface, timer/counter, time-base timer, vector interrupt, on- screen display function, i 2 c bus interface, pwm generator, remote control receiver, hsync counter, and watchdog timer. also, the CXP854P60 provides power-on reset and sleep functions. the designers have ensured low power consumption for these powerful micro- computers. incorporating a one-time prom, the CXP854P60 has an equivalent function to the cxp85460 and character rom for osd can be written. therefore, it is suitable for evaluation in system development and for the production of small amounts. features instruction set which supports a wide array of data types-213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean operations. minimum instruction cycle 0.5s/8mhz on-chip prom 60k bytes (for program) 10k bytes (for osd) on-chip ram 960 bytes on-screen display function 12 18 dots, 384 types, 12lines of 32 characters black frame output, half blanking, shadow, background color on full screen double scanning mode supported includes jitter elimination circuit i 2 c bus interface 14-bit pwm output, 8-bit pwm output (8 channels) remote control receiver circuit 8-bit a/d converter (4 channels, 20s conversion time/4mhz, 8mhz) hsync counter (2channels) watchdog timer 8-bit synchronized serial i/o 8-bit timer, 8-bit timer/counter, 19-bit time-base timer general purpose input/output 32-line i/o (bit-selectable input/output), also 6-line input, 10-line output (internal 8-line nch-o/d) interrupts 13 factors, 13 vectors, multiple interrupt possible standby mode sleep package 64-pin plastic sdip/qfp purchase of sony's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. ?1 CXP854P60 e95109a16-ps cmos 8-bit single-chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (piastic) 64 pin qfp (piastic) structure silicon gate cmos ic
?2 CXP854P60 on screen display serial i/o timer/counter remocon fifo a/d converter i 2 c interface unit watch dog timer 14bit pwm 8 bit pwm 8ch clock gen./ system control ram 960 bytes spc700 cpu core prom 60k prescaler/ time base timer port a port b port c port d port e port f 2 2 v ss v dd mp rst xtal extal pd0/int2 pe1/int1 pe0/int0 pf0/pwm0 to pf7/pwm7 interrupt controller pe6/pwm pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pe6 to pe7 pf0 to pf7 xlc exlc r g b i ys ym pa7/hsync pa6/vsync pd3/si pd2/so pd1/sck pd7/ec pe7/to pd6/rmc pd4/hs0 pd5/hs1 pe2/an0 to pe5/an3 pf4/scl0 pf5/scl1 pf6/sda0 pf7/sda1 hsync counter 0 hsync counter 1 vpp block diagram
3 CXP854P60 hsync/pa7 vsync/pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ec/pd7 rmc/pd6 hs1/pd5 hs0/pd4 si/pd3 so/pd2 sck/pd1 v ss v dd vpp v ss mp pf0/pwm0 pf1/pwm1 pf2/pwm2 pf3/pwm3 pf4/pwm4/scl0 pf5/pwm5/scl1 pf6/pwm6/sda0 pf7/pwm7/sda1 ym ys i b g r exlc xlc pe0/int0 pe1/int1 pe2/an0 pe3/an1 pe4/an2 pe5/an3 pe6/pwm pe7/to rst extal xtal pd0/int2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 pin assignment (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ec/pd7 pf3/pwm3 pf4/pwm4/scl0 pf5/pwm5/scl1 pf6/pwm6/sda0 pf7/pwm7/sda1 ym ys i b g r exlc xlc pe0/int0 pe1/int1 pe2/an0 pe3/an1 pe4/an2 pe5/an3 rmc/pd6 hs1/pd5 hs0/pd4 si/pd3 so/pd2 sck/pd1 v ss int2/pd0 xtal extal rst to/pe7 pwm/pe6 pa2 pa3 pa4 pa5 pa6/vsync pa7/hsync v ss v dd vpp mp pf0/pwm0 pf1/pwm1 pf2/pwm2 29 note) 1. vpp pin 63 must be connected to v dd . 2. vss pins 32 and 62 must have a common gnd. 3. mp pin 61 must be connected to gnd. note) 1. vpp pin 56 must be connected to v dd . 2. vss pins 26 and 58 must have a common gnd. 3. mp pin 55 must be connected to gnd.
4 CXP854P60 (port a) single bit selectable 8-bit port. (8 lines) (port b) single bit selectable 8-bit port. (8 lines) (port c) single bit selectable 8-bit port. (8 lines) (port d) single bit selectable 8-bit port. 12ma sink current drive possible. (8 lines) (port e) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 lines) (port f) 8-bit output port with large current (12ma) n-ch open drain output. lower 4 bits middle voltage tolerance (12v), upper 4 bits 5v suppression. (8 lines) crt display 6-bit output pin. pin functions pin name pa0 to pa5 pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/int0 pe1/int1 pe2/an0 to pe5/an3 pe6/pwm pe7/to pf0/pwm0 to pf3/pwm3 pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 r, g, b, i, ys, ym i/o i/o/input i/o/input i/o i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input input/input input/input output/output output/output output/output output/output/ i/o output/output/ i/o output i/o function crt display vertical synchronization signal input pin. crt display horizontal synchronization signal input pin. input pin for external interrupt request. active on falling edge. serial clock pin. serial data output pin. serial data input pin. hsync counter (ch0) input pin. hsync counter (ch1) input pin. remote control receiver circuit input pin. external event timer/counter input pin. input pin for external interrupt request. active falling edge. (2 lines) analog input pin for a/d converter. (4 lines) 14-bit pwm output pin. (cmos output) square wave output for timer 1. (50% duty cycle) 8-bit pwm output pin. (8-lines) i 2 c bus interface transfer clock i/o pin. i 2 c bus interface transfer data i/o pin.
5 CXP854P60 pin name exlc xlc extal xtal rst mp vpp v dd vss input output input output i/o input crt display clock oscillator i/o pin. oscillator frequency is determined external l, c circuit. system clock oscillator crystal connection pin. when using an external clock, input to extal pin and leave xtal pin open. "l" level active system reset. this pin also acts as an i/o pin during power up. while internal power-on reset function is talking place a "l" level is output. test mode input pin. must be connected to gnd. positive power supply pin for incorporated prom writing. under normal operating conditions, connect to v dd . positive supply voltage pin. gnd. both vss pins should be connected to common gnd. i/o function
6 CXP854P60 data bus rd (port a, b, c) aa aa ip aa aa input protection circuit aaaa a aa a aaaa port a data port b data port c data aaaa aaaa port a direction port b direction port c direction data bus rd (port a) aa aa ip aa aa schmitt input aaaa aaaa port a direction aaaa aaaa port a data input protection circuit aaaa input multiplexer vsync hsync data bus rd (port d) aa aa ip aa aa aaaa aaaa port d direction aaaa aaaa port d data large current source 12ma int2, si, hs0, hs1, rmc, ec schmitt input pin equivalent i/o circuit port a port b port c port a port d 22 lines 2 lines 6 lines hi-z hi-z hi-z pin when reset circuit format pa0 to pa5 pb0 to pb7 pc0 to pc7 pa6/vsync pa7/hsync pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec
7 CXP854P60 data bus rd (port d) aa aa ip aa aa aaaa port d direction aaaa port d data large current source 12ma schmitt input sck only sck or so output enable aa aa aa ip rd (port e) data bus schmitt input (to interrupt circuit) aa aa aa aa ip input multiplexer to a/d converter rd (port e) data bus to, pwm aaaaa port e selection aaaaa aa port e data port d port e 2 lines 2 lines 4 lines 2 lines pin when reset circuit format pe0/int0 pe1/int1 port e port e hi-z hi-z hi-z h level pe2/an0 to pe5/an3 pd1/sck pd2/so pe6/pwm pe7/to
8 CXP854P60 scl, sda aaaaa aaaaa port f selection aaaaa aaaaa aa aa port f data large current source 12ma pwm i 2 c output enable a a ip schmitt input scl, sda (to i 2 c circuit) to other i 2 c pins bus sw pwm aaaaa aaaaa port f selection aaaaa aaaaa aa aa port f data 12v voltage torelance large current source 12ma port f port f 4 lines 4 lines 6 lines 2 lines pin when reset circuit format pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 hi-z hi-z hi-z oscillation halted r g b i ys ym pf0/pwm0 to pf3/pwm3 exlc xlc aa aa r, g, b, i, ys, ym to output polarity register writing data to port register brings output from high impedance to active aaaa aaaa output polarity oscillator control aa aa exlc aa aa a a ip crt display clock aa aa ip xlc
9 CXP854P60 2 lines 1 line pin when reset circuit format rst oscillation l level extal xtal aa aa aa ip aa extal xtal diagram indicates equivalent circuit during oscillation feedback resistor is disconnected during stop aa aa schmitt input pull-up resistor from power-on reset circuit
10 CXP854P60 ? 1 v in and v out should not exceed v dd + 0.3v. ? 2 the large current driver for the pd and pf ports is a n-ch transistor. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium voltage tolerance output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd vpp v in v out v outp i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +13.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 0.3 to +15.0 5 50 15 20 130 10 to +75 55 to +150 1000 600 v v v v v ma ma ma ma ma c c mw mw incorporated prom pins pf0 to pf3 total of all output pins excludes large current output large current output ? 2 total of all output pins sdip qfp item symbol ratings unit remarks absolute maximum ratings (vss = 0v) supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.5 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 10 vpp v ih v ihs v ihex v il v ils v ilex topr safe operating range safe operating range for low speed data ? 1 safe operating range for data retention during stop ? 5 i 2 c schmitt input included ? 2 cmos schmitt input ? 3 extal pin ? 4 i 2 c schmitt input included ? 2 cmos schmitt input ? 3 extal pin ? 4 v dd ? 1 rating for 1/16 frequency mode and sleep mode. ? 2 normal input port (all pins pa, pb, pc, pe2 to pe5), pf4 to pf7 pins. ? 3 includes pd0/int2, pd1/sck, pd2, pd3/si, pd4/hs0, pd5/hs1, pd6/rmc, pd7/ec, pe0/int0, pe1/int1, hsync, vsync, rst pins. ? 4 rating applies to external clock input only. ? 5 vpp and v dd should be set to a same voltage. recommended operating conditions (vss =0v) vpp = v dd
11 CXP854P60 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain output leak current (n-ch tr off case) i 2 c bus switch connection impedance (output tr off case) supply current input capacitance 4.0 3.5 20 1.0 10 3 20 a pf 50 10 120 35 ma ma a a ? 0.4 0.6 1.5 0.4 0.6 40 40 400 10 v v v v v a a a a 0.5 0.5 1.5 v v pa to pd, pe6, pe7, r, g, b, i, ys, ym pa to pd, pe6, pe7, r, g, b, i, ys, ym, pf0 to pf3, rst pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst pa to pe, hsync, vsync, r, g, b, i, ys, ym pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd ? 1 operating mode (1/2, clock rate) 8mhz crystal oscillator (c 1 = c 2 = 22pf) all output pins open stop mode ? 2 sleep mode pins other than v dd and vss 1mhz clock 0v for non-measurement pins item symbol pin condition min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst c in i ihe i ihl i ilr dc characteristics (ta = 10 to +75 c, vss = 0v) ? 1 rating applies only if osd oscillator is halted. ? 2 this device does not enter in the stop mode.
12 CXP854P60 ac characteristics (1) clock timing ? t sys indicates one of three values according to the contents of the clock control register. (for cpu clock selection.) t sys (ns) = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") system clock frequency system clock input pulse width system clock rise and fall times event counter input clock pulse widtth event counter input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item system pin condition min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig 1, fig 2 external clock drive fig. 3 fig. 3 3.5 50 t sys + 50 ? 9 200 20 (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) fig. 1. clock timing extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc fig. 2. clock applied condition aaaaa a aaa a aaaaa aaaaa a aaa a aaaaa crystal oscillator ceramic oscillator extal xtal external clock extal xtal open c 1 c 2 fig. 3. event count clock timing ec t eh t el t ef t er 0.2v dd 0.8v dd
13 CXP854P60 (2) serial transfer (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input set-up time (referenced to sck ) si input hold time (referenced to sck ) sck so delay time system pin condition min. max. unit note) for sck output mode, in addition to output delay time so capacitance must be 50pf + 1ttl. fig. 4. serial transfer timing 0.2v dd 0.8v dd t kl t kh so t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si sck
14 CXP854P60 external interrupt high and low level widths reset input low level width int0 to int2 rst 1 8/fc s s item symbol pin condition min. max. unit t ih t il t rsl power supply rise time power supply cutt-off time t r t off v dd power-on reset repeated power-on reset 0.05 1 50 ms ms item symbol pin condition min. max. unit (3) interrupt, reset input (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) (4) power-on reset power on reset (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 to int2 (falling edge) 0.2v 0.2v 4.5v v dd t r t off take care when turning on power. fig. 5. interrupt input timing t rsl 0.2v dd rst fig. 6. rst input timing fig. 7. power-on reset
15 CXP854P60 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt ? 1 v ft ? 2 t conv t samp v ian an0 to an3 ta = 25 c v dd = 5.0v vss = 0v 10 4910 160/f adc ? 3 12/f adc ? 3 0 10 4970 8 1 70 5030 v dd bits lsb mv mv s s v item symbol pin condition min. typ. max. unit (5) a/d converter characteristics (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) linearity error v zt v ft analog input ff h fe h 01 h 00 h digital conversion value fig. 8. definitions for a/d converter terms ? 1 v zt : digital conversion values change between 00 h 01 h . ? 2 v ft : digital conversion values change between 0e h 0f h . ? 3 f adc indicates the below values due to the bit6 (cks) of a/d control registor (address: 00f6 h ) and the bit 7 (pck1) and bit 6 (pck0) of clock control registor (address: 00fe h ) 00 ( = f ex /2) 01 ( = f ex /4) 11 ( = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 f adc = f c cks pck1, 0 0 ( /2 selection) 1 ( /2 selection) f adc = f c /2 f adc = f c /8
16 CXP854P60 (6) i 2 c bus timing (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item scl clock frequency bus free time before starting transfer hold time for starting transfer clock low level width clock high level width set-up time for repeated transfers data hold time data set-up time sda, scl rise time sda, scl fall time set-up time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 ? 0.25 4.7 100 1 0.3 khz s s s s s s s s s s symbol pin condition min. max. unit ? since scl rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns. fig. 9. i 2 c bus transfer data timing p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 10. i 2 c device suggested circuit i 2 c device i 2 c device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor must be connected to sda0 (or sda1), and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 ? or less) can be used to reduce spike noise caused by crt flashover.
17 CXP854P60 (7) osd (on screen display) timing (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item osd clock frequency hsync pulse width hsync afterwrite rise and fall times vsync afterwrite rise and fall times f osc t hwd t hcg t vcg exlc xlc hsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 4 1.2 7 ? 1 14 ? 2 200 1.0 4 1.2 mhz s ns s 11 ? 1 16 ? 2 200 1.0 symbol pin condiiton unit shadow existent min. max. min. max. shadow non-existent ? 1 oscillator clock at 4mhz operation ? 2 oscillator clock at 8mhz operation fig. 11. osd timing 0.8v dd 0.2v dd t hcg t hwd hsync for opol register (01fa h ) bit 7 at 0 0.8v dd 0.2v dd t vcg vsync for opol register (01fa h ) bit 6 at 0 fig. 12. lc oscillator circuit connection l c 2 c 1 exlc xlc
18 CXP854P60 supplement fig. 13. spc700 series recommended oscillation circuit aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (i) aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (ii) manufacturer murata mfg co., ltd. kinseki ltd. model csa4.00mg csa4.19mg csa8.00mtz cst4.00mgw ? cst4.19mgw ? cst8.00mtw ? hc-49/u03 hc-49/u(-s) fc (mhz) 4.00 4.19 8.00 4.00 4.19 8.00 4.00 4.19 8.00 4.00 4.19 8.00 30 12 30 12 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (ii) (i) 27 27 0 (i) ? indicates types with on-chip grounding capacitors (c 1 and c 2 ). product list river eletec co., ltd. option item package program rom capacitance reset pin pull-up resistor power-on reset circuit font data 64-pin plastic sdip/qfp 52k/60k byte existent/non-existent existent/non-existent user specified 64-pin plastic sdip/qfp prom 60k byte existent existent user specified (prom) ? mask product CXP854P60s-1- CXP854P60q-1- ? the font data for the one-time prom version is operated in the same way as the program writing.
19 CXP854P60 fig. 14. characteristics curves 23 1 45 6 0.1 10 15 10 8 6 4 2 0 100 10 0 l inductance [h] parameter curve for osd oscillator l vs. c (analytically calculated value) 50 100 c 1 , c 2 capacitance [pf] 5.0mhz 6.5mhz 13.0mhz v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 8mhz, ta = 25 c, typical) fc system clock [mhz] i dd vs. fc (v dd = 5v, ta = 25 c, typical) 1/2 frequency mode sleep mode 1/4 frequency mode 1/16 frequency mode 1/2 frequency mode 1/4 frequency mode 1/16 frequency mode sleep mode 20 16 14 12 10 i dd supply current [ma] 18 f osc = c = c 1 // c 2 1 2 lc
20 CXP854P60 package outline unit: mm 64pin sdip (plastic) min 0.5 min 3.0 4.75 ?0.1 0.9 0.15 0.5 0.1 0.25 ?0.05 + 0.1 17.1 ?0.1 19.05 132 33 64 1.778 57.6 ?0.1 + 0.4 package material lead treatment lead material package mass epoxy resin 42/copper alloy sony code eiaj code jedec code sdip-64p-01 p-sdip64-17.1x57.6-1.778 solder plating 8.6g + 0.3 + 0.3 0? to 15? package structure 64pin sdip (plastic) min 0.5 min 3.0 4.75 0.1 0.9 0.15 0.5 0.1 0.25 0.05 + 0.1 17.1 0.1 19.05 132 33 64 1.778 57.6 0.1 + 0.4 package material lead treatment lead material package mass epoxy resin 42/copper alloy sony code eiaj code jedec code sdip-64p-01 p-sdip64-17.1x57.6-1.778 solder plating 8.6g + 0.3 + 0.3 0 ? to 15 ? package structure lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.
21 CXP854P60 package outline unit: mm sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 ? to10 ? lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony corporation

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